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277 lines
9.1 KiB
277 lines
9.1 KiB
/*
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u8x8_d_ssd1326.c
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Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)
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Copyright (c) 2016, olikraus@gmail.com
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or other
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materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "u8x8.h"
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/* ER OLED */
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static const uint8_t u8x8_d_ssd1326_er_256x32_init_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_CA(0x0fd, 0x012), /* unlock (not required, this is default by reset) */
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U8X8_C(0x0ae), /* display off */
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U8X8_CA(0x0a8, 0x01f), /* multiplex ratio: 0x03f * 1/64 duty - changed by CREESOO, acc. to datasheet, 100317*/
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U8X8_CA(0x0a1, 0x000), /* display start line */
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U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
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U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
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/*
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a0 command: 0x0a0 ***abcde
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a: 1: mono mode
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b: 0: horizontal (1: vertical) address increment
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c: 1: enable bit remap
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d: 1: COM remap
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e: 1: Column remap
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*/
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U8X8_CA(0x0a0, 0x006), /* remap configuration, see above */
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U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
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U8X8_C(0x0b7), /* set default gray scale table */
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U8X8_CA(0x081, 0x027), /* contrast, brightness, 0..128 */
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U8X8_CA(0x0b1, 0x071), /* phase length */
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//U8X8_CA(0x0b2, 0x051), /* frame frequency (row period) */
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U8X8_CA(0x0b3, 0x0f0), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
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//U8X8_CA(0x0b4, 0x002), /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
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//U8X8_CA(0x0b0, 0x028), /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
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U8X8_CAA(0x0bb, 0x035, 0x0ff), /* set precharge */
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U8X8_CA(0x0bc, 0x01f), /* pre-charge voltage level */
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U8X8_CA(0x0be, 0x00f), /* VCOMH voltage */
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U8X8_CA(0x0bf, 0x002|0x00d), /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
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U8X8_C(0x0a4), /* normal display mode */
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//U8X8_CA(0x023, 0x003), /* graphics accelleration: fill pixel */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1326_256x32_nhd_powersave0_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_C(0x0af), /* display on */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1326_256x32_nhd_powersave1_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_C(0x0ae), /* display off */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1326_256x32_nhd_flip0_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_CA(0x0a0, 0x006), /* remap 00110 */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1326_256x32_nhd_flip1_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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//U8X8_CA(0x0a0, 0x005), /* remap 00101 */
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U8X8_CA(0x0a0, 0x001), /* remap 00001 */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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/*
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input:
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one tile (8 Bytes)
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output:
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Tile for ssd1326 (32 Bytes)
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*/
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static uint8_t u8x8_ssd1326_8to32_dest_buf[32];
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static uint8_t *u8x8_ssd1326_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)
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{
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uint8_t v;
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uint8_t a,b;
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uint8_t i, j;
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uint8_t *dest;
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for( j = 0; j < 4; j++ )
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{
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dest = u8x8_ssd1326_8to32_dest_buf;
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dest += j;
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a =*ptr;
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ptr++;
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b = *ptr;
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ptr++;
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for( i = 0; i < 8; i++ )
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{
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v = 0;
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if ( a&1 ) v |= 0xf0;
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if ( b&1 ) v |= 0x0f;
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*dest = v;
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dest+=4;
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a >>= 1;
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b >>= 1;
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}
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}
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return u8x8_ssd1326_8to32_dest_buf;
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}
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static uint8_t u8x8_d_ssd1326_256x32_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
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{
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uint8_t x, y, c;
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uint8_t *ptr;
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switch(msg)
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{
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/* handled by the calling function
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case U8X8_MSG_DISPLAY_SETUP_MEMORY:
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u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1326_256x32_nhd_display_info);
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break;
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*/
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case U8X8_MSG_DISPLAY_INIT:
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u8x8_d_helper_display_init(u8x8);
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1326_er_256x32_init_seq);
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break;
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case U8X8_MSG_DISPLAY_SET_POWER_SAVE:
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if ( arg_int == 0 )
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1326_256x32_nhd_powersave0_seq);
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else
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1326_256x32_nhd_powersave1_seq);
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break;
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case U8X8_MSG_DISPLAY_SET_FLIP_MODE:
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if ( arg_int == 0 )
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{
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1326_256x32_nhd_flip0_seq);
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u8x8->x_offset = u8x8->display_info->default_x_offset;
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}
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else
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{
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1326_256x32_nhd_flip1_seq);
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u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
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}
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break;
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#ifdef U8X8_WITH_SET_CONTRAST
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case U8X8_MSG_DISPLAY_SET_CONTRAST:
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u8x8_cad_StartTransfer(u8x8);
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u8x8_cad_SendCmd(u8x8, 0x081 );
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u8x8_cad_SendArg(u8x8, arg_int ); /* ssd1326 has range from 0 to 255 */
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u8x8_cad_EndTransfer(u8x8);
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break;
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#endif
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case U8X8_MSG_DISPLAY_DRAW_TILE:
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u8x8_cad_StartTransfer(u8x8);
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x = ((u8x8_tile_t *)arg_ptr)->x_pos;
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x *= 4;
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y = (((u8x8_tile_t *)arg_ptr)->y_pos);
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y *= 8;
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y += u8x8->x_offset; /* x_offset is used as y offset for the ssd1326 */
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do
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{
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c = ((u8x8_tile_t *)arg_ptr)->cnt;
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ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;
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do
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{
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u8x8_cad_SendCmd(u8x8, 0x015 ); /* set column address */
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u8x8_cad_SendArg(u8x8, x ); /* start */
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u8x8_cad_SendArg(u8x8, x+3 ); /* end */
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u8x8_cad_SendCmd(u8x8, 0x075 ); /* set row address */
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u8x8_cad_SendArg(u8x8, y);
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u8x8_cad_SendArg(u8x8, y+7);
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u8x8_cad_SendData(u8x8, 32, u8x8_ssd1326_8to32(u8x8, ptr));
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ptr += 8;
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x += 4;
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c--;
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} while( c > 0 );
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//x += 4;
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arg_int--;
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} while( arg_int > 0 );
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u8x8_cad_EndTransfer(u8x8);
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break;
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default:
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return 0;
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}
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return 1;
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}
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static const u8x8_display_info_t u8x8_ssd1326_256x32_display_info =
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{
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/* chip_enable_level = */ 0,
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/* chip_disable_level = */ 1,
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/* post_chip_enable_wait_ns = */ 20,
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/* pre_chip_disable_wait_ns = */ 15,
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/* reset_pulse_width_ms = */ 100,
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/* post_reset_wait_ms = */ 100, /**/
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/* sda_setup_time_ns = */ 100, /* ssd1326 */
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/* sck_pulse_width_ns = */ 100, /* ssd1326 */
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/* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
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/* spi_mode = */ 0, /* active high, rising edge */
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/* i2c_bus_clock_100kHz = */ 4,
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/* data_setup_time_ns = */ 40,
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/* write_pulse_width_ns = */ 60, /* ssd1326 */
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/* tile_width = */ 32,
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/* tile_height = */ 4,
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/* default_x_offset = */ 0, /* x_offset is used as y offset for the ssd1326 */
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/* flipmode_x_offset = */ 0, /* x_offset is used as y offset for the ssd1326 */
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/* pixel_width = */ 256,
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/* pixel_height = */ 32
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};
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uint8_t u8x8_d_ssd1326_er_256x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
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{
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if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
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{
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u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1326_256x32_display_info);
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return 1;
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}
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return u8x8_d_ssd1326_256x32_generic(u8x8, msg, arg_int, arg_ptr);
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}
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